Low Power Digital Clock Design Using LVCMOS Input/Output Standards on 45nm FPGA

摘要

How wonderful it would be if every device we use is energy efficient. This is an approach to design an efficient digital clock that consumes low amount of power. This is done by varying frequency to different levels and checking corresponding amount of energy consumed. Low Voltage Complementary metal oxide semiconductor i.e. LVCMOS and 45nm Spartan-6 FPGA family is used for simulation and amount of total power consumed is noted down. There is 90.02%, 98.88%, 99.86% and 100% reduction in the clock when we scale down frequency from 100GHz to 10GHz, 1GHz, 0.1GHz, and 0.01GHz respectively.